Digital signal processing for wireless communications, such as digital baseband processing or digital front-end implementations, can be implemented using some hardware (e.g. silicon) computing platforms. For example, multimedia processing and digital radio frequency (RF) processing may be accomplished in a digital front-end implementation of a wireless transceiver, as implemented by an application-specific integrated circuit (ASIC). A variety of hardware platforms can implement such digital signal processing, such as the ASIC, a digital signal processor (DSP) implemented as part of a field-programmable gate array (FPGA), or a system-on-chip (SoC). However, each of these solutions often requires implementing customized signal processing methods that are hardware implementation specific. For example, a digital signal processor can implement a turbocoding application for data in a customized design of an FPGA.
Many traditional digital signal processing systems implement a dual-chip solution in which a network on chip is implemented on one integrated circuit chip and coupled to an antenna tuned for a particular frequency range. The network on chip is coupled to a host chip on a separate integrated circuit chip over a communications bus (e.g., a Peripheral Component Interconnect Express bus). However, such systems are physically larger and draw substantial power, which limits their applicability to wireless and/or mobile applications, such as smartphones, tablets, and laptop computers.
Moreover, there is interest in moving wireless communications to “fifth generation” (5G) systems. 5G offers promise of increased speed and ubiquity, but methodologies for processing 5G wireless communications have not yet been set.